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@ -55,9 +55,13 @@ module id(input wire rst,
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imm <= `ZeroWord;
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case (op)
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`EXE_ORI: begin
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wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
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alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
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imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
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wreg_o <= `WriteEnable;
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aluop_o <= `EXE_OR_OP;
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alusel_o <= `EXE_RES_LOGIC;
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reg1_read_o <= 1'b1;
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reg2_read_o <= 1'b0;
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imm <= {16'h0, inst_i[15:0]};
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wd_o <= inst_i[20:16];
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instvalid <= `InstValid;
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end
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default: begin
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@ -72,7 +76,7 @@ module id(input wire rst,
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reg1_o <= `ZeroWord;
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end else if ((reg1_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg1_addr_o)) begin
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reg1_o <= ex_wdata_i;
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end else if ((reg1_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg1_addr_o)) begin
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end else if ((reg1_read_o == 1'b1)&&(mem_wreg_i == 1'b1)&&(mem_wd_i == reg1_addr_o)) begin
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reg1_o <= mem_wdata_i;
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end else if (reg1_read_o == 1'b1) begin
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reg1_o <= reg1_data_i;
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@ -88,7 +92,7 @@ module id(input wire rst,
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reg2_o <= `ZeroWord;
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end else if ((reg2_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg2_addr_o)) begin
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reg2_o <= ex_wdata_i;
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end else if ((reg2_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg2_addr_o)) begin
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end else if ((reg2_read_o == 1'b1)&&(mem_wreg_i == 1'b1)&&(mem_wd_i == reg2_addr_o)) begin
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reg2_o <= mem_wdata_i;
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end else if (reg2_read_o == 1'b1) begin
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reg2_o <= reg2_data_i;
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