From 79240e91b101a9c53d9e105230faeb6837fa386e Mon Sep 17 00:00:00 2001 From: YunMao Date: Mon, 25 Mar 2019 14:57:54 +0800 Subject: [PATCH] =?UTF-8?q?=E8=A7=A3=E5=86=B3=E6=95=B0=E6=8D=AE=E7=9B=B8?= =?UTF-8?q?=E5=85=B3=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Src/id.v | 16 ++++++++++------ Src/inst_rom.v | 2 +- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/Src/id.v b/Src/id.v index 3bf13d1..60e8024 100644 --- a/Src/id.v +++ b/Src/id.v @@ -55,10 +55,14 @@ module id(input wire rst, imm <= `ZeroWord; case (op) `EXE_ORI: begin - wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP; - alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0; - imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16]; - instvalid <= `InstValid; + wreg_o <= `WriteEnable; + aluop_o <= `EXE_OR_OP; + alusel_o <= `EXE_RES_LOGIC; + reg1_read_o <= 1'b1; + reg2_read_o <= 1'b0; + imm <= {16'h0, inst_i[15:0]}; + wd_o <= inst_i[20:16]; + instvalid <= `InstValid; end default: begin end @@ -72,7 +76,7 @@ module id(input wire rst, reg1_o <= `ZeroWord; end else if ((reg1_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg1_addr_o)) begin reg1_o <= ex_wdata_i; - end else if ((reg1_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg1_addr_o)) begin + end else if ((reg1_read_o == 1'b1)&&(mem_wreg_i == 1'b1)&&(mem_wd_i == reg1_addr_o)) begin reg1_o <= mem_wdata_i; end else if (reg1_read_o == 1'b1) begin reg1_o <= reg1_data_i; @@ -88,7 +92,7 @@ module id(input wire rst, reg2_o <= `ZeroWord; end else if ((reg2_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg2_addr_o)) begin reg2_o <= ex_wdata_i; - end else if ((reg2_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg2_addr_o)) begin + end else if ((reg2_read_o == 1'b1)&&(mem_wreg_i == 1'b1)&&(mem_wd_i == reg2_addr_o)) begin reg2_o <= mem_wdata_i; end else if (reg2_read_o == 1'b1) begin reg2_o <= reg2_data_i; diff --git a/Src/inst_rom.v b/Src/inst_rom.v index e68cd76..9324d43 100644 --- a/Src/inst_rom.v +++ b/Src/inst_rom.v @@ -6,7 +6,7 @@ module inst_rom(input wire ce, reg[`InstBus] inst_mem[0:`InstMemNum-1]; - initial $readmemh ("D:/Codings/Vivado/MIPS/inst_rom.data", inst_mem); + initial $readmemh ("D:/Desktop/Examples-in-book-write-your-own-cpu-master/Code/Chapter5_1/AsmTest/inst_rom.data", inst_mem); always @ (*) begin if (ce == `ChipDisable) begin