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@ -5,6 +5,12 @@ module id(input wire rst,
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input wire[`InstBus] inst_i,
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input wire[`RegBus] reg1_data_i,
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input wire[`RegBus] reg2_data_i,
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input wire ex_wreg_i, //EX
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input wire[`RegBus] ex_wdata_i,
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input wire[`RegAddrBus] ex_wd_i,
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input wire mem_wreg_i, //MEM
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input wire[`RegBus] mem_wdata_i,
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input wire[`RegAddrBus] mem_wd_i,
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output reg reg1_read_o,
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output reg reg2_read_o,
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output reg[`RegAddrBus] reg1_addr_o,
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@ -64,6 +70,10 @@ module id(input wire rst,
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always @ (*) begin
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if (rst == `RstEnable) begin
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reg1_o <= `ZeroWord;
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end else if ((reg1_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg1_addr_o)) begin
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reg1_o <= ex_wdata_i;
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end else if ((reg1_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg1_addr_o)) begin
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reg1_o <= mem_wdata_i;
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end else if (reg1_read_o == 1'b1) begin
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reg1_o <= reg1_data_i;
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end else if (reg1_read_o == 1'b0) begin
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@ -76,6 +86,10 @@ module id(input wire rst,
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always @ (*) begin
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if (rst == `RstEnable) begin
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reg2_o <= `ZeroWord;
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end else if ((reg2_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg2_addr_o)) begin
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reg2_o <= ex_wdata_i;
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end else if ((reg2_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg2_addr_o)) begin
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reg2_o <= mem_wdata_i;
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end else if (reg2_read_o == 1'b1) begin
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reg2_o <= reg2_data_i;
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end else if (reg2_read_o == 1'b0) begin
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