verilog-format

Src/yunmips.v

@@ -1,10 +1,10 @@
 `include "../Defines.v"
 
 module yunmips(input wire clk,
-                input wire rst,
-                input wire[`RegBus] rom_data_i,
-                output wire[`RegBus] rom_addr_o,
-                output wire rom_ce_o);
+               input wire rst,
+               input wire[`RegBus] rom_data_i,
+               output wire[`RegBus] rom_addr_o,
+               output wire rom_ce_o);
     
     wire[`InstAddrBus] pc;
     wire[`InstAddrBus] id_pc_i;