From c91e5b52fd806c147a1a76ab4c4504ec423798ee Mon Sep 17 00:00:00 2001
From: YunMao <13325803302@126.com>
Date: Mon, 25 Mar 2019 10:31:59 +0800
Subject: [PATCH] verilog-format

---
 Src/yunmips.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Src/yunmips.v b/Src/yunmips.v
index 89f4ec3..e83b90d 100644
--- a/Src/yunmips.v
+++ b/Src/yunmips.v
@@ -1,10 +1,10 @@
 `include "../Defines.v"
 
 module yunmips(input wire clk,
-                input wire rst,
-                input wire[`RegBus] rom_data_i,
-                output wire[`RegBus] rom_addr_o,
-                output wire rom_ce_o);
+               input wire rst,
+               input wire[`RegBus] rom_data_i,
+               output wire[`RegBus] rom_addr_o,
+               output wire rom_ce_o);
     
     wire[`InstAddrBus] pc;
     wire[`InstAddrBus] id_pc_i;