From 52411d3efbd48f9a2295a79e4b2f8178f4d02c01 Mon Sep 17 00:00:00 2001
From: YunMao <13325803302@126.com>
Date: Mon, 25 Mar 2019 11:40:15 +0800
Subject: [PATCH] =?UTF-8?q?=E6=95=B0=E6=8D=AE=E5=89=8D=E6=8E=A8=E6=B5=8B?=
 =?UTF-8?q?=E8=AF=95=E6=A1=88=E4=BE=8B?=
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---
 Src/id.v      | 14 ++++++++++++++
 Src/yunmips.v |  8 ++++++++
 2 files changed, 22 insertions(+)

diff --git a/Src/id.v b/Src/id.v
index 63965e9..3bf13d1 100644
--- a/Src/id.v
+++ b/Src/id.v
@@ -5,6 +5,12 @@ module id(input wire rst,
           input wire[`InstBus] inst_i,
           input wire[`RegBus] reg1_data_i,
           input wire[`RegBus] reg2_data_i,
+          input wire ex_wreg_i,                //EX
+          input wire[`RegBus] ex_wdata_i,
+          input wire[`RegAddrBus] ex_wd_i,
+          input wire mem_wreg_i,               //MEM
+          input wire[`RegBus] mem_wdata_i,
+          input wire[`RegAddrBus] mem_wd_i,
           output reg reg1_read_o,
           output reg reg2_read_o,
           output reg[`RegAddrBus] reg1_addr_o,
@@ -64,6 +70,10 @@ module id(input wire rst,
     always @ (*) begin
         if (rst == `RstEnable) begin
             reg1_o <= `ZeroWord;
+            end else if ((reg1_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg1_addr_o)) begin
+            reg1_o <= ex_wdata_i;
+            end else if ((reg1_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg1_addr_o)) begin
+            reg1_o <= mem_wdata_i;
             end else if (reg1_read_o == 1'b1) begin
             reg1_o <= reg1_data_i;
             end else if (reg1_read_o == 1'b0) begin
@@ -76,6 +86,10 @@ module id(input wire rst,
     always @ (*) begin
         if (rst == `RstEnable) begin
             reg2_o <= `ZeroWord;
+            end else if ((reg2_read_o == 1'b1)&&(ex_wreg_i == 1'b1)&&(ex_wd_i == reg2_addr_o)) begin
+            reg2_o <= ex_wdata_i;
+            end else if ((reg2_read_o == 1b'1)&&(mem_wreg_i == 1b'1)&&(mem_wd_i == reg2_addr_o)) begin
+            reg2_o <= mem_wdata_i;
             end else if (reg2_read_o == 1'b1) begin
             reg2_o <= reg2_data_i;
             end else if (reg2_read_o == 1'b0) begin
diff --git a/Src/yunmips.v b/Src/yunmips.v
index e83b90d..c2c9ac8 100644
--- a/Src/yunmips.v
+++ b/Src/yunmips.v
@@ -73,6 +73,14 @@ module yunmips(input wire clk,
     
     .reg1_data_i(reg1_data),
     .reg2_data_i(reg2_data),
+
+    .ex_wreg_i(ex_wreg_o),                //EX
+    .ex_wdata_i(ex_wdata_o),
+    .ex_wd_i(ex_wd_o),
+
+    .mem_wreg_i(mem_wreg_o),               //MEM
+    .mem_wdata_i(mem_wdata_o),
+    .mem_wd_i(mem_wd_o),
     
     .reg1_read_o(reg1_read),
     .reg2_read_o(reg2_read),