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27 lines
694 B
27 lines
694 B
`include "../Defines.v"
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module mem_wb(input wire clk,
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input wire rst,
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input wire[`RegAddrBus] mem_wd,
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input wire mem_wreg,
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input wire[`RegBus] mem_wdata,
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output reg[`RegAddrBus] wb_wd,
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output reg wb_wreg,
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output reg[`RegBus] wb_wdata);
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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wb_wd <= `NOPRegAddr;
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wb_wreg <= `WriteDisable;
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wb_wdata <= `ZeroWord;
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end else begin
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wb_wd <= mem_wd;
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wb_wreg <= mem_wreg;
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wb_wdata <= mem_wdata;
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end
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end
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endmodule
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