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26 lines
388 B
26 lines
388 B
`include "../Defines.v"
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`timescale 1ns/1ps
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module yunmips_min_sopc_tb();
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reg CLOCK_50;
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reg rst;
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initial begin
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CLOCK_50 = 1'b0;
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forever #10 CLOCK_50 = ~CLOCK_50;
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end
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initial begin
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rst = `RstEnable;
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#195 rst= `RstDisable;
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#1000 $stop;
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end
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yunmips_min_sopc yunmips_min_sopc0(
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.clk(CLOCK_50),
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.rst(rst)
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);
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endmodule |