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89 lines
2.8 KiB
89 lines
2.8 KiB
`include "../Defines.v"
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module id(input wire rst,
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input wire[`InstAddrBus] pc_i,
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input wire[`InstBus] inst_i,
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input wire[`RegBus] reg1_data_i,
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input wire[`RegBus] reg2_data_i,
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output reg reg1_read_o,
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output reg reg2_read_o,
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output reg[`RegAddrBus] reg1_addr_o,
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output reg[`RegAddrBus] reg2_addr_o,
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output reg[`AluOpBus] aluop_o,
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output reg[`AluSelBus] alusel_o,
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output reg[`RegBus] reg1_o,
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output reg[`RegBus] reg2_o,
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output reg[`RegAddrBus] wd_o,
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output reg wreg_o);
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wire[5:0] op = inst_i[31:26];
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wire[4:0] op2 = inst_i[10:6];
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wire[5:0] op3 = inst_i[5:0];
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wire[4:0] op4 = inst_i[20:16];
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reg[`RegBus] imm;
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reg instvalid;
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always @ (*) begin
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if (rst == `RstEnable) begin
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aluop_o <= `EXE_NOP_OP;
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alusel_o <= `EXE_RES_NOP;
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wd_o <= `NOPRegAddr;
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wreg_o <= `WriteDisable;
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instvalid <= `InstValid;
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reg1_read_o <= 1'b0;
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reg2_read_o <= 1'b0;
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reg1_addr_o <= `NOPRegAddr;
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reg2_addr_o <= `NOPRegAddr;
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imm <= 32'h0;
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end else begin
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aluop_o <= `EXE_NOP_OP;
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alusel_o <= `EXE_RES_NOP;
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wd_o <= inst_i[15:11];
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wreg_o <= `WriteDisable;
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instvalid <= `InstInvalid;
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reg1_read_o <= 1'b0;
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reg2_read_o <= 1'b0;
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reg1_addr_o <= inst_i[25:21];
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reg2_addr_o <= inst_i[20:16];
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imm <= `ZeroWord;
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case (op)
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`EXE_ORI: begin
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wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
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alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
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imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
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instvalid <= `InstValid;
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end
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default: begin
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end
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endcase
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end
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end
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always @ (*) begin
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if (rst == `RstEnable) begin
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reg1_o <= `ZeroWord;
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end else if (reg1_read_o == 1'b1) begin
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reg1_o <= reg1_data_i;
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end else if (reg1_read_o == 1'b0) begin
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reg1_o <= imm;
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end else begin
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reg1_o <= `ZeroWord;
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end
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end
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always @ (*) begin
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if (rst == `RstEnable) begin
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reg2_o <= `ZeroWord;
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end else if (reg2_read_o == 1'b1) begin
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reg2_o <= reg2_data_i;
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end else if (reg2_read_o == 1'b0) begin
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reg2_o <= imm;
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end else begin
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reg2_o <= `ZeroWord;
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end
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end
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endmodule
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