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47 lines
1.1 KiB
47 lines
1.1 KiB
`include "../Defines.v"
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module ex(input wire rst,
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input wire[`AluOpBus] aluop_i,
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input wire[`AluSelBus] alusel_i,
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input wire[`RegBus] reg1_i,
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input wire[`RegBus] reg2_i,
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input wire[`RegAddrBus] wd_i,
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input wire wreg_i,
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output reg[`RegAddrBus] wd_o,
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output reg wreg_o,
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output reg[`RegBus] wdata_o);
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reg[`RegBus] logicout;
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always @ (*) begin
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if (rst == `RstEnable) begin
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logicout <= `ZeroWord;
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end else begin
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case (aluop_i)
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`EXE_OR_OP:
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begin
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logicout <= reg1_i | reg2_i;
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end
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default:
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begin
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logicout <= `ZeroWord;
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end
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endcase
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end
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end
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always @ (*) begin
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wd_o <= wd_i;
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wreg_o <= wreg_i;
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case (alusel_i)
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`EXE_RES_LOGIC: begin
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wdata_o <= logicout;
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end
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default: begin
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wdata_o <= `ZeroWord;
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end
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endcase
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end
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endmodule
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