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56 lines
1.7 KiB
56 lines
1.7 KiB
`include "../Defines.v"
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module regfile(input wire clk,
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input wire rst,
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input wire we,
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input wire[`RegAddrBus] waddr,
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input wire[`RegBus] wdata,
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input wire re1,
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input wire[`RegAddrBus] raddr1,
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output reg[`RegBus] rdata1,
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input wire re2,
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input wire[`RegAddrBus] raddr2,
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output reg[`RegBus] rdata2);
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reg[`RegBus] regs[0:`RegNum-1];
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always @ (posedge clk) begin
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if (rst == `RstDisable) begin
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if ((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
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regs[waddr] <= wdata;
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end
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end
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end
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always @ (*) begin
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if (rst == `RstEnable) begin
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rdata1 <= `ZeroWord;
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end else if (raddr1 == `RegNumLog2'h0) begin
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rdata1 <= `ZeroWord;
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end else if ((raddr1 == waddr) && (we == `WriteEnable)
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&& (re1 == `ReadEnable)) begin
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rdata1 <= wdata;
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end else if (re1 == `ReadEnable) begin
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rdata1 <= regs[raddr1];
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end else begin
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rdata1 <= `ZeroWord;
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end
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end
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always @ (*) begin
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if (rst == `RstEnable) begin
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rdata2 <= `ZeroWord;
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end else if (raddr2 == `RegNumLog2'h0) begin
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rdata2 <= `ZeroWord;
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end else if ((raddr2 == waddr) && (we == `WriteEnable)
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&& (re2 == `ReadEnable)) begin
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rdata2 <= wdata;
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end else if (re2 == `ReadEnable) begin
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rdata2 <= regs[raddr2];
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end else begin
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rdata2 <= `ZeroWord;
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end
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end
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endmodule
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