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25 lines
530 B
25 lines
530 B
`include "../Defines.v"
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module pc_reg(input wire clk,
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input wire rst,
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output reg[`InstAddrBus] pc,
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output reg ce);
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always @ (posedge clk) begin
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if (ce == `ChipDisable) begin
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pc <= 32'h00000000;
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end else begin
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pc <= pc + 4'h4;
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end
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end
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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ce <= `ChipDisable;
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end else begin
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ce <= `ChipEnable;
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end
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end
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endmodule
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