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27 lines
616 B
27 lines
616 B
`include "../Defines.v"
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module mem(input wire rst,
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input wire[`RegAddrBus] wd_i,
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input wire wreg_i,
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input wire[`RegBus] wdata_i,
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output reg[`RegAddrBus] wd_o,
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output reg wreg_o,
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output reg[`RegBus] wdata_o);
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always @ (*) begin
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if (rst == `RstEnable) begin
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wd_o <= `NOPRegAddr;
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wreg_o <= `WriteDisable;
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wdata_o <= `ZeroWord;
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end
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else begin
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wd_o <= wd_i;
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wreg_o <= wreg_i;
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wdata_o <= wdata_i;
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end
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end
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endmodule
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