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21 lines
527 B
21 lines
527 B
`include "../Defines.v"
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module if_id(input wire clk,
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input wire rst,
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input wire[`InstAddrBus] if_pc,
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input wire[`InstBus] if_inst,
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output reg[`InstAddrBus] id_pc,
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output reg[`InstBus] id_inst);
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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id_pc <= `ZeroWord;
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id_inst <= `ZeroWord;
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end else begin
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id_pc <= if_pc;
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id_inst <= if_inst;
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end
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end
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endmodule
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