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37 lines
1.1 KiB
37 lines
1.1 KiB
`include "../Defines.v"
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module id_ex(input wire clk,
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input wire rst,
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input wire[`AluOpBus] id_aluop,
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input wire[`AluSelBus] id_alusel,
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input wire[`RegBus] id_reg1,
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input wire[`RegBus] id_reg2,
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input wire[`RegAddrBus] id_wd,
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input wire id_wreg,
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output reg[`AluOpBus] ex_aluop,
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output reg[`AluSelBus] ex_alusel,
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output reg[`RegBus] ex_reg1,
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output reg[`RegBus] ex_reg2,
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output reg[`RegAddrBus] ex_wd,
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output reg ex_wreg);
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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ex_aluop <= `EXE_NOP_OP;
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ex_alusel <= `EXE_RES_NOP;
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ex_reg1 <= `ZeroWord;
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ex_reg2 <= `ZeroWord;
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ex_wd <= `NOPRegAddr;
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ex_wreg <= `WriteDisable;
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end else begin
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ex_aluop <= id_aluop;
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ex_alusel <= id_alusel;
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ex_reg1 <= id_reg1;
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ex_reg2 <= id_reg2;
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ex_wd <= id_wd;
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ex_wreg <= id_wreg;
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end
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end
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endmodule
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