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28 lines
701 B
28 lines
701 B
`include "../Defines.v"
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module ex_mem(input wire clk,
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input wire rst,
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input wire[`RegAddrBus] ex_wd,
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input wire ex_wreg,
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input wire[`RegBus] ex_wdata,
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output reg[`RegAddrBus] mem_wd,
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output reg mem_wreg,
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output reg[`RegBus] mem_wdata);
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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mem_wd <= `NOPRegAddr;
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mem_wreg <= `WriteDisable;
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mem_wdata <= `ZeroWord;
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end
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else begin
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mem_wd <= ex_wd;
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mem_wreg <= ex_wreg;
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mem_wdata <= ex_wdata;
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end
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end
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endmodule
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