逻辑、移位和空

master
YunMao 5 years ago
parent 79240e91b1
commit 1e19295f30

@ -1,4 +1,4 @@
//global
//ȫ<EFBFBD><EFBFBD>
`define RstEnable 1'b1
`define RstDisable 1'b0
`define ZeroWord 32'h00000000
@ -26,35 +26,31 @@
`define ChipDisable 1'b0
//instruction
`define EXE_ORI 6'b001101 // ORI
`define EXE_AND 6'b100100 // AND
`define EXE_OR 6'b100101 // OR
`define EXE_XOR 6'b100110 // XOR
`define EXE_NOR 6'b100111 // NOR
`define EXE_ANDI 6'b001100 // ANDI
`define EXE_ORI 6'b001101 // ORI
`define EXE_XORI 6'b001110 // XORI
`define EXE_LUI 6'b001111 // LUI
`define EXE_SLL 6'b000000 // SLL
`define EXE_SLLV 6'b000100 // SLLV
`define EXE_SRL 6'b000010 // SRL
`define EXE_SRLV 6'b000110 // SRLV
`define EXE_SRA 6'b000011 // SRA
`define EXE_SRAV 6'b000111 // SRAV
`define EXE_SYNC 6'b001111 // SYNC
`define EXE_PREF 6'b110011 // PREF
`define EXE_NOP 6'b000000 // NOP
`define EXE_SPECIAL_INST 6'b000000 // SPECIAL
`define EXE_MOVZ 6'b001010
`define EXE_MOVN 6'b001011
`define EXE_MFHI 6'b010000
`define EXE_MTHI 6'b010001
`define EXE_MFLO 6'b010010
`define EXE_MTLO 6'b010011
//ָ<EFBFBD><EFBFBD>
`define EXE_AND 6'b100100
`define EXE_OR 6'b100101
`define EXE_XOR 6'b100110
`define EXE_NOR 6'b100111
`define EXE_ANDI 6'b001100
`define EXE_ORI 6'b001101
`define EXE_XORI 6'b001110
`define EXE_LUI 6'b001111
`define EXE_SLL 6'b000000
`define EXE_SLLV 6'b000100
`define EXE_SRL 6'b000010
`define EXE_SRLV 6'b000110
`define EXE_SRA 6'b000011
`define EXE_SRAV 6'b000111
`define EXE_SYNC 6'b001111
`define EXE_PREF 6'b110011
`define EXE_NOP 6'b000000
`define SSNOP 32'b00000000000000000000000001000000
`define EXE_SPECIAL_INST 6'b000000
`define EXE_REGIMM_INST 6'b000001
`define EXE_SPECIAL2_INST 6'b011100
//AluOp
`define EXE_AND_OP 8'b00100100
@ -75,29 +71,21 @@
`define EXE_NOP_OP 8'b00000000
`define EXE_MOVZ_OP 8'b00001010
`define EXE_MOVN_OP 8'b00001011
`define EXE_MFHI_OP 8'b00010000
`define EXE_MTHI_OP 8'b00010001
`define EXE_MFLO_OP 8'b00010010
`define EXE_MTLO_OP 8'b00010011
//AluSel
`define EXE_RES_LOGIC 3'b001
`define EXE_RES_SHIFT 3'b010
`define EXE_RES_MOVE 3'b011
`define EXE_RES_NOP 3'b000
//inst_rom
//ָ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>inst_rom
`define InstAddrBus 31:0
`define InstBus 31:0
`define InstMemNum 131071
`define InstMemNumLog2 17
//regfile
//ͨ<EFBFBD>üĴ<EFBFBD><EFBFBD><EFBFBD>regfile
`define RegAddrBus 4:0
`define RegBus 31:0
`define RegWidth 32
@ -106,4 +94,3 @@
`define RegNum 32
`define RegNumLog2 5
`define NOPRegAddr 5'b00000

@ -12,6 +12,8 @@ module ex(input wire rst,
output reg[`RegBus] wdata_o);
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
always @ (*) begin
if (rst == `RstEnable) begin
logicout <= `ZeroWord;
@ -21,6 +23,18 @@ module ex(input wire rst,
begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP:
begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP:
begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP:
begin
logicout <= reg1_i ^ reg2_i;
end
default:
begin
logicout <= `ZeroWord;
@ -29,15 +43,39 @@ module ex(input wire rst,
end
end
always @ (*) begin
if (rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case (alusel_i)
`EXE_RES_LOGIC: begin
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
default: begin
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase

@ -54,7 +54,83 @@ module id(input wire rst,
reg2_addr_o <= inst_i[20:16];
imm <= `ZeroWord;
case (op)
`EXE_ORI: begin
`EXE_SPECIAL_INST: begin
case (op2)
5'b00000: begin
case (op3)
`EXE_OR: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_AND: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_XOR: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_NOR: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_NOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLLV: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRLV: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRAV: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SYNC: begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin
end
endcase
end
default: begin
end
endcase
end
`EXE_ORI: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
@ -64,9 +140,78 @@ module id(input wire rst,
wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ANDI: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]};
wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_XORI: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]};
wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_LUI: begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {inst_i[15:0], 16'h0};
wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_PREF: begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
default: begin
end
endcase
if (inst_i[31:21] == 11'b00000000000) begin
if (op3 == `EXE_SLL) begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6];
wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end else if (op3 == `EXE_SRL) begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6];
wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end else if (op3 == `EXE_SRA) begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6];
wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end
end
end
end

@ -6,7 +6,7 @@ module inst_rom(input wire ce,
reg[`InstBus] inst_mem[0:`InstMemNum-1];
initial $readmemh ("D:/Desktop/Examples-in-book-write-your-own-cpu-master/Code/Chapter5_1/AsmTest/inst_rom.data", inst_mem);
initial $readmemh ("D:/Codings/Vivado/YunMIPS-D/inst_rom.data", inst_mem);
always @ (*) begin
if (ce == `ChipDisable) begin

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